OK-MX9352-UP4_User Hardware Design Guide_V1.0
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Overview
This document corresponds to the UP4 SoM product, describing the schematic design of the UP4 peripheral circuits, PCB design, troubleshooting approaches for common interface issues, design features of functional interfaces, and more. It assists engineers in quickly familiarizing themselves with the product, facilitating maintenance and development tasks.
The designs provided in this document are for guidance only. During application design, please adapt your designs based on actual scenarios and conditions. For any inquiries, please contact our company’s technical support.
Revision History
Date |
Version |
Revision History |
|---|---|---|
02/03/2026 |
V1.0 |
Initial Version |
Application Scope
This hardware manual applies to the UP4 Forlinx SoM
1. Schematic Design
1.1 Schematic Design Guidelines for UP4 Carrier Board
All pins must be designed according to the voltage levels specified in the UP4 Pin Definition Table. Pins without special requirements below can be directly connected, provided the voltage levels are compatible.
1. Pin (1/2) Signal Name (VCC5V) Design Requirements
The main power supply pins for the System on Module (SoM) on the carrier board should be connected to a non-switched 5V power source from the carrier board, which must be capable of delivering 3A (15W) specifically for the SoM alone. If the carrier board also uses this power source, the total required current will be the sum of 3A plus the current demand of the carrier board.
Additionally, a redundancy margin of at least 20% of the system’s peak power consumption (SoM + carrier board) must be maintained. Therefore, the 5V power source should provide a minimum of ≥ (15W + Carrier board peak power) * 120%.
It is essential to add filter capacitors to the carrier board before supplying the 5V signal to the SoM. Recommended capacitor values include 100nF, 1μF, 10μF, and 22μF.
Diagram:
2. Pin (4) Signal Name (EXTP_EN) Design Requirements
When designing the carrier board, use this pin to manage the power-up sequence. This pin is configured as a push-pull output on the System-on-Module (SoM). By default, there should be a pull-down resistor on the carrier board, and the power to the carrier board should remain off initially. The power should only turn on when the SoM sends a high signal on this pin. Additionally, the power supplies on the carrier board must have soft-start functionality to prevent inrush current spikes during power-up.
Design Reference:
1. Control the Power MOSFET to Turn on the Controlled Power Supply on the carrier board:
To achieve this, an RC soft-start circuit must be added. The designated pin controls the AO3416, which regulates the operation of the power MOSFET. It’s essential to include both pull-up and pull-down resistors to ensure that both MOSFETs remain off by default. Refer to Figure 1 for further details.
2. Directly Control the DC-DC Enable Pin:
For DC-DC circuits that have built-in soft-start functionality, this pin can be connected directly to the circuit’s EN signal. A series resistor must be added to ensure the correct electrical current is maintained. Verify whether the pin’s default state is low or whether the DC-DC circuit is disabled by default. See Figure2.
Figure 1
Figure 2
3. Pin Number (5), Signal Name (STANDBY) Design Requirements
The power supply of specific circuits on the carrier board can be controlled using this pin, enabling low-power mode to be implemented in certain scenarios. It controls the conduction of a MOSFET and a pull-down resistor ensures an inactive state by default (i.e. the MOSFET is turned on and power is supplied). When the relevant conditions are met, the SoM turns off the power to certain circuits on the carrier board by setting the output high. An RC soft-start circuit is required.
4. Pin Number (6), Signal Name (nRESET) Design Requirements
The design of the carrier board must not include any pull-up resistors. The SoM provides the high-level state. The carrier board is connected to a switch button to achieve low-level triggering. The debounce capacitor and TVS tube can be omitted as required.
Diagram:
5. Pin Number (7), Signal Name (WAKEUP) Design Requirements
The design of the carrier board must not include any pull-up resistors. The SoM provides the high-level state. The carrier board is connected to a switch button to achieve low-level triggering. The debounce capacitor and TVS tube can be omitted as required.
Diagram:
6. Pin Number (8), Signal Name (PWRON) Design Requirements
The design of the carrier board must not include any pull-up resistors. The SoM provides the high-level state. The carrier board is connected to a switch button to achieve low-level triggering. The debounce capacitor and TVS tube can be omitted as required.
Diagram:
7. Pin Numbers (9/10), Signal Names (BOOT1/BOOT2) Design Requirements
The design of the carrier board involves the two BOOT pins being pulled down to ground. This is achieved through the use of a 1K resistor, which is connected to the pins via a dual-position DIP switch. The use of pull-up resistors or other circuits is not permitted. The switch configurations are as follows:
BOOT MOD |
BOOT1 |
BOOT0 |
|---|---|---|
EMMC |
OFF |
OFF |
TF |
OFF |
ON |
NOR |
ON |
OFF |
NAND |
ON |
ON |
Diagram:
8. Pin Number (11), Signal Name (FORCE_USBLOAD) Design Requirements
The design of the carrier board must not include any pull-up resistors. The SoM provides the high-level state. The carrier board is connected to a switch button to achieve low-level triggering. The debounce capacitor and TVS tube can be omitted as required.
Diagram:
9. Pin Number (12), Signal Name (POR_B) Design Requirements
It is used to reset the CPU and should only be used in conjunction with the JTAG interface for CPU debugging.
10.Pin Number（34/35/69/70/325/326）Signal Name（I2C）Design Requirements
When designing this pin, it’s essential to add pull-up resistors to the carrier board. Additionally, a 0Ω resistor should be placed before each connected chip to facilitate debugging. If this I2C bus is shared with the SoM, it’s advisable to minimize or avoid using this I2C bus in the carrier board design as much as possible. If you do use it, ensure that there are no address conflicts with the SoM. Furthermore, the hardware manual for this platform specifies the addresses of devices connected to the SoM, the appropriate values for the pull-up resistors, and which other functions cannot be reused.
11. Display Interface (LCD/LVDS/MIPI_DSI/HDMI/EDP) Design Requirements
Pin Numbers (191/163/164/358/175/359/371/370), Signal Names (LCD_PWR_EN/PWM_B/LVDS_PWR_EN/PWM_A/EDP_PWR_EN/PWM_C/MIPI_PWR_EN/PWM_D): When designing a carrier board, it is essential to connect the pins to their respective display interfaces according to their classification. Each pin requires a pull-down resistor to ensure it defaults to a low level when the system is powered on, enabling it to be pulled high under System on Module (SoM) control. This setup helps to prevent screen flickering during power-up. If an enable (EN) signal is absent, the corresponding display interface should be pulled up directly. PWM signals also require pull-down resistors to prevent screen flickering at power-on.
Pin Numbers (271/272/364/365/274/275/178/179/361/362), Pin Names (EDP_TX_AUX/EDP_TX_D0/EDP_TX_D1/EDP_TX_D2/EDP_TX_D3): When designing a carrier board, it is essential to add DC-blocking capacitors. For the AUX pair, allocate a P-side pull-down resistor and an N-side pull-up resistor.
12. Ethernet Interface (RGMII/RMII) Design Requirements
Pin numbers (284 and 215) and pin names (RGMII_A_RST and RGMII_B_RST) should be connected to the chip’s reset pin through a series resistor. Additionally, an RC circuit must be included to ensure that the PHY resets correctly, even when this signal is not present on the System on Module (SoM).
Pin Numbers (86/87/103/104), Pin Names (RGMII_A_MDIO/RGMII_A_MDC/RGMII_B_MDIO/RGMII_B_MDC): Series resistors are required, and pull-up resistors must be added (the pull-up on the clock line can be left unpopulated).
All signal pins need to be connected to the PHY via series resistors for future debugging purposes.
13. SD Card Interface Design Requirements
Once all the signals have been connected to the SD and TF card slots, series resistors should be added and positioned close to the stamp holes for debugging purposes. Power should be supplied via SoM pin 118 and the SD_A_PWR pin, with filtering capacitors connected near the slots. Do not use the carrier board power supply.
14. SDIO Interface Design Requirements
For future debugging purposes, all signal pins need to be connected to the Wi-Fi via series resistors. The BT_HOST_WAKE_B and WIFI_HOST_WAKE_B signals must use the dedicated pins on the SoM to ensure sleep/wake-up functionality. Other control signals can use regular GPIOs.
15. PCIe Interface Design Requirements
All TX signal pins should have series capacitors added on the carrier board connecting to the PCIe slot. All RX signal pins should have series resistors added on the carrier board connecting to the PCIe slot. The clock signals for Group A can be provided either by the carrier board or the SoM to ensure support for both RC and EP modes. The clock signal pins for Group B should have series resistors added on the carrier board connecting to the PCIe slot.
16. USB Interface Design Requirements
Pin Numbers (298/295), Pin Names (USB2_A_VBUS/USB2_B_VBUS): When designing a carrier board, the 5V power supply must be connected to these pins. In HOST mode, the carrier board supplies the power, whereas in DEVICE mode, the socket supplies the power. A power switching control circuit is also required.
Pin Numbers (299/296), Pin Names (USB2_A_ID/USB2_B_ID): When designing a carrier board, only the pull-down function should be retained; do not add pull-ups. The SoM provides the high-level state.
For signal pins: When connecting to the socket, USB 2.0 signals must have series resistors reserved. For USB 3.0, TX signals require DC-blocking capacitors (series capacitors) and RX signals require series resistors.
17. JTAG Interface Design Requirements
All data pins must have reserved pull-up resistors. The pull-up voltage must match the VREF of the JTAG interface.
1.2 UP4 Platform Carrier Board Schematic Compatibility Design Guide
At present, five platforms are compatible with the UP4 platform. RK3568, RK3562, T527, T536 and MX9352. As these platforms have different interfaces, any compatibility design must include redundancy to support switching between them.
1. Reserved Design for Display Interfaces
The UP4 definition supports five display interfaces: LVDS, LCD, MIPI_DSI, HDMI, and eDP. For the enable pins of these display interfaces, it is necessary to reserve RC or series resistors. This ensures that the screen can be enabled normally on platforms where extra I/O pins are unavailable.
The HDMI interface’s I2C and CEC must be compatible with 3.3 V or 5 V levels.
2. Camera Module Design
If the Master Clock (MCLK) output from the System on Module (SoM) is required, the design should reserve series and voltage divider resistors to ensure the clock signal level meets the requirements of the camera module.
A total of 27 MHz active clock must be reserved for four analogue camera modules to provide a clock source when the SoM has no MCLK resource.
3. WiFi Module Design
To ensure compatibility with different I/O levels, power supplies for both 3.3V and 1.8V should be reserved, as well as for the crystal oscillator. The appropriate active crystal oscillator should be selected based on the actual voltage in use. Additionally, a divider resistor should be used to match the level of the signal control.
4. Gigabit Ethernet Port Design
The IO level of 3.3 V and 1.8 V is to be considered, as well as the level selection option, pull-up level option, and network port status light option, which are to be reserved. In order to be compatible with the RMII interface, the RMII chip must be designed so that the signal line can be selectively soldered through the resistor.
5. Audio Codec Design
To ensure compatibility with 1.8V and 3.3V I/O levels, both 3.3V and 1.8V I/O power supplies should be reserved. The signal pins should also be configured to support both I/O states, selectable via series resistors. Additionally, a 24M active clock should be reserved for the MCLK signal to accommodate platforms without built-in MCLK.
In the PCB BOM, for the USB port, the dual-layer USB socket or single-layer USB socket can be selected for soldering through package compatibility.
2. PCB Design
2.1 PCB Compatibility Design Examples
1. Ethernet Port Compatibility Design Example
2.2 U40 Carrier Board PCB Layout Design Guidelines
This specification can be applied to different PCB designs. You can refer to it and make optimization based on your actual use.
1. Stack-up Configuration
For 4-layer boards, the recommended stack-up is: S1 - POWER - GND - S2. The impedance profile is as shown below:
For 6-layer boards, the recommended stack-up is: S1 - GND - S2 - S3 - POWER - S4. The impedance profile is as shown below:
The specific stack-up can be adjusted according to actual requirements.
2. Via Configuration
The preferred via size series:
Hole Size 24mil 20mil 16mil 12mil 8mil Pad Diameter: 40mil 35mil 28mil 25mil 20mil
For the LGA fanout, a 12/20 mil via configuration is recommended.
3. Routing Layout
As the SoM uses LGA pins predominantly, and most high-speed signals and all differential pairs are located in the LGA area, signals from the LGA should be fanned out collectively and primarily routed on the bottom layer to ensure signal integrity. This is shown in the figure below:
The fan-out method for LGA differential pairs is illustrated below:
A minimum safety spacing of three times the trace width (3W) should be maintained between differential pairs to prevent signal crosstalk. If conditions permit, it is recommended to implement ground isolation around the differential pairs, as shown in the figure below.
For the LGA differential line pad area on the carrier board, the first two reference layers of the carrier board need to be partially voided to ensure impedance continuity. Please refer to the figure below for the specific voiding area.
For the stamp hole, after completing the normal routing on the top layer, the traces are switched to the bottom layer to ensure that the entire group can be collectively rerouted after exiting.
Schematic of the direction change:
Single-ended 50-ohm impedance traces must maintain at least 2.5W clearance to prevent crosstalk.
The overall routing is as follows:
4. Stencil and Component Placement Requirements
The stencil layer for carrier board footprints is custom-designed. Don’t do modifications to the stencil layer design. The stencil is expanded in the stamp-hole areas. No vias are allowed within these stencil expansion zones. The stencil design is shown below:
Do not place any components within 5 mm of the board edge (i.e. outside the outer yellow frame in the diagram below). This area is reserved for the stencil used in the separate soldering process for the System on Module (SoM). The size of this keep-out area may be modified based on practical use.
